Conventional semiconductor IC (integrated circuit) memory devices are designed to operate at fixed data I/O widths. For example, in a processing system having an 8-bit data bus, 8-bit data words can be stored to, or retrieved from, a memory in a single memory access cycle (referred to as “X8 operation”).
For example, FIG. 1A schematically illustrates a conventional semiconductor IC memory device (1) having a fixed I/O width. In general, the semiconductor IC memory device (1) comprises a first address input buffer (10), a row decoder (20), a column decoder (30), a second address input buffer (40), a command buffer (50), a memory cell array (60), a sense amplifier array (70), a data output buffer (80) and a data input buffer (90). The semiconductor IC memory device (1) further comprises eight data output pins (DOUT0˜DOUT7) connected to the data output buffer (80) for outputting an 8-bit data word (Data_Out <0:7>) that is read from the memory (60), as well as eight data input pins (DIN0˜DIN7) for inputting an 8-bit data word (Data_In <0:7>) that is to be written to the memory (60).
The first address input buffer (10) buffers a 9-bit external address signal (ADDR<0:8>) that is latched in from address lines, which can be either a column address signal or the first nine bits of a row address signal that is latched in with, e.g., a column address strobe (CAS) or a row address strobe (RAS), respectively. In the exemplary embodiment of FIG. 1, it is assumed that the row address bits (RA<0:8>) and column address bits (CA <0:8>) are multiplexed through the same address pins to minimize the number of pins required for interfacing with an address bus. The second address input buffer (40) buffers the last two bits (ADDR <9:10>) of the external row address signal. The row decoder (20) decodes the row address bits (RA <0:10>) received from the buffers (10) and (40) and generates a wordline signal (WL) to access a row of memory cells in the memory array (60) corresponding to the row address bits (RA<0:10>). The column decoder (30) decodes the column address bits (CA<0:8>) received from the buffer (10) to generate a column select signal (CSL) for accessing a block of memory locations within the accessed row, which in the exemplary embodiment of FIG. 1A, is a storage location corresponding to a group of 8 blocks.
Depending on whether a read or write operation is being performed as indicated by the input command (READ, WRITE) that is buffered by command buffer (50), an 8-bit data word (Data_Out<0:7>) is read from the accessed storage location, or an 8-bit data word (Data_In<0:7>) is written to the accessed storage location. The sense amplifier array (70) enables data to be read or written to the memory cell array (60).
The data output buffer (80) comprises a plurality of output buffers (81˜88) for buffering a data word (Data_Out <0:7>) that is read from the memory cell array (60) during a read operation. The data input buffer (90) comprises a plurality of input buffers (91˜98) that buffer a data word (Data_In <0:7>) to be written to the memory cell array (60) during a write operation. Each output buffer (81˜88) is connected to a corresponding one of the data output pins (DOUT0˜DOUT7) and each input buffer (91˜98) is connected to a corresponding one of the data input pins (DIN0˜DIN7) (although in another embodiment as depicted in FIG. 1B, a plurality of data I/O pins (DQ0˜DQ7) are connected to corresponding ones of the output buffers (81˜88) and the input buffers (91˜98) and are used for both data input and data output).
As noted above, the conventional semiconductor IC memory device (1) provides a fixed X8 operation, i.e., an 8-bit data word is read from or written to the memory (60) during a single memory access operation. More specifically, FIG. 2 is an exemplary timing diagram illustrating a method for outputting data during a memory read operation of the semiconductor IC memory device (1). As illustrated in FIG. 2, a read command (READ) and a column address (CA) are input synchronously with a clock CLK signal at clock cycle C1 (it is assumed that a wordline has already been activated). In response, an 8-bit data word comprising bits Q0˜Q7 are simultaneously output from the output buffer (80) to the respective output pins (DOUT0˜DOUT7) about 2 clock cycles after the read command and column address are input.
Furthermore, FIG. 3 is an exemplary timing diagram illustrating a method for inputting data during a memory write operation of the semiconductor IC memory device (1). As illustrated in FIG. 3, a write command (WRITE) and a column address (CA) are input synchronously with a clock CLK signal at clock cycle C1 (it is assumed that a wordline has already been activated). In response, an 8-bit data word comprising bits D0˜D7 are simultaneously input to the data input buffer (90) from the respective data input pins (DIN0˜DIN7), in the same clock cycle C1 as the write command and the column address are input.
Conventional semiconductor memory devices such as described above, which employ fixed data I/O width control schemes can only perform read, write or active operations at the fixed I/O width. Such conventional semiconductor memory device designs are inefficient when used with systems or applications in which data words are not equal to, or multiples of, the fixed data I/O width. For instance, RGB (Red, Green Blue) data for notebook PC and mobile applications (cellular phones, PDA, etc) is represented by 18 bits (each component, R, G and B, comprises a 6-bit data word (X6)), whereas RGB data for desktop computers (PC) and servers is represented by 24 bits (each component, R, G and B, comprises an 8-bit data word (X8)). In such instance, if such notebook PC and mobile applications were used with a memory system having a fixed X8 operation, such applications would be processing 6 redundant data bits, i.e., at least 24 data bits would have to be accessed for an 18-bit data block. Such redundancy would result in unnecessary power consumption in such devices/applications due to processing of such redundant bits.